1. Field of the Invention
The present invention relates to a semiconductor device and a method for producing the same, more specifically this invention relates to a semiconductor device to effectively prevent the body floating effect and various related problems in MOS field effect transistors formed on a SOI (silicon-on-insulator) substrate, and a method for easily producing the semiconductor device.
2. Description of Related Art
A semiconductor device having various elements such as transistors formed on a single crystalline silicon layer formed on an insulator is known as a structure called SOI (Silicon On Insulator). The structure shown in FIG. 2 for example is disclosed on page 755 of the Extended Abstracts (the Spring Meeting, 1995) The Japan Society of Applied Physics and Related Societies. The MOS field effect transistor (hereafter simply referred to as MOS) is formed on a single crystalline silicon (Si) layer 3 separated from a handle wafer 1 by a thick insulator 2. The reference numeral 4 in FIG. 2 indicates a device isolation layer, the numeral 5 indicates a gate insulator, the numeral 6 is a gate electrode, the numeral 7 is a gate electrode protection insulator, the numeral 8 is a gate side-wall insulator, the numerals 9 and 10 are n-type highly concentrated impurity diffusion regions with respective drain and source regions.
The special feature of SOI-MOS of the conventional art as shown in FIG. 2, is that a thick device insulation layer 2, is present directly beneath the single crystalline silicon (Si) layer 3 so that the parasitic wiring capacitance and the drain junction capacitance are reduced to approximately one-tenth of the capacitance of an ordinary MOS formed on an Si substrate. Another feature is that the MOS is also isolated by insulation from the handle wafer 1 so that misoperation due to alpha ray beam irradiation and latch-up phenomenon are essentially eliminated.
However, in an SOI-MOS device of this type, the single crystalline silicon (Si) layer 3 is completely isolated from the handle wafer 1 so that minority carriers (holes) generated for example, by the strong electrical field of the drain tend to transiently accumulate within the single crystalline silicon (Si) layer 3 and cause a shifting threshold voltage or so-called body floating effect. This body floating effect can be viewed as the parasitic bipolar effect that causes majority carriers to flow in as a result of a rise in electrical potential due to accumulation of minority carriers within the single crystalline silicon (Si) layer 3. In n-channel SOI-MOS devices, (hereafter abbreviated to n-SOI-MOS) the threshold voltage fluctuates in the negative direction due to the accumulated holes and an abnormal bump can be observed in the device current/voltage characteristics (kink characteristic). This condition causes problems such as a large leakage current when the device is in the off state and a lowering the source and drain breakdown voltage which can be a fatal defect in differential amplifiers and analog circuits which must detect tiny differences in the electrical current.
In the SOI-MOS device shown in FIG. 2, in order to prevent the above mentioned body floating effect, germanium (Ge) is ion-implanted into a source highly concentrated impurity diffusion region 9 and a SiGe alloy 14 with a Ge content of approximately 10 percent is formed. FIG. 3 shows the energy band diagram along the channel when a voltage is applied to the drain of the SOI-MOS device in FIG. 2. In FIG. 3, EFn is the pseudo-fermi level and Ei is the intrinsic fermi level. The bandgap narrows by approximately 0.1 eV by forming the SiGe alloy 14, the valence band Ev for the source is formed as shown by the broken line, and the difference in hole diffusion potential is reduced. As a result, the holes generated near the drain and accumulating within the single crystalline silicon (Si) layer 3 tend to diffuse within the source and be eliminated. The conduction band Ec is unaffected by the SiGe alloy 14 and there are no adverse effects on the behavior of electrons which are majority carriers.
However, due to control of the valence band at the source junction the structure shown in FIG. 2 is inadequate for eliminating the body floating effect in p-channel SOI-MOS devices (hereafter abbreviated to pSOI-MOS), and when germanium (Ge) is introduced into the source region of the pSOI-MOS device, the difference in diffusion potential drops and the breakdown voltage deteriorates. Further, in nSOI-MOS devices since the body floating effect cannot be adequately eliminated, and an excessive amount of germanium (Ge) of more than 10 percent is injected into the source region, the problem of crystalline defects occurs due to the difference in lattice constants of the Si (silicon) and Ge (germanium). The only way to eliminate the crystalline defects is to reduce the Ge (germanium) content however, the improved drop in diffusion potential does not amount to more than approximately 0.1 eV which is inadequate to eliminate the body floating effect.
The SOI-MOS device of FIG. 4 is disclosed on page 627 of the Extended Abstracts of the 1995 International Electron Devices Meeting and the SOI-MOS device of FIG. 5 is disclosed on page 337 of the Extended Abstracts of the 1992 International Electron Devices Meeting.
In the SOI-MOS device of FIG. 4, after forming the source and drain diffusion regions 9 and 10, argon (Ar) is ion-implanted and a recombination center region 15 formed within the source and drain, and the holes that accumulated inside the single crystalline silicon (Si) layer 3 are eliminated. However, unless the position of the recombination center region 15 versus the drain junction is optimal, then the leakage current tends to increase so that also eliminating the holes within the single crystalline silicon (Si) layer 3 is extremely difficult.
In the SOI-MOS device of FIG. 5 however, a portion of the junction of the bottom of the source 9 is destroyed by a spike 16 resulting from abnormal diffusion of a metal electrode and the holes within the single crystalline silicon (Si) layer 3 are eliminated by this spike 16. In this structure, in order to maintain a flow path for the positive holes, from the single crystalline silicon (Si) layer 3, a portion below the bottom of the source 9 is used as the P-type highly concentrated impurity region, and a portion below the drain 10 is used as an N-type highly concentrated impurity region to prevent the spike 16 from causing a deterioration in the transistor characteristics. As a result, the source 9 and the drain 10 are not symmetrical and the device is not usable in general purpose.
Accordingly it is an object of the present invention to resolve the above mentioned problems with the SOI-MOS device of the conventional art in FIG. 2, by providing an SOI-MOS device having a new structure and a production method for this device, applicable even to p-SOI-MOS devices as well as complementary SOI-MOS devices and further capable of preventing crystalline defects in the active region and the body floating effect.
It is a further object of the present invention to resolve the above mentioned problems with the SOI-MOS device of the conventional art in FIG. 4, by providing an SOI-MOS device having a new structure and a production method for this device, to stop the occurrence of defects in the active regions of the source and drain and also adequately prevent the body floating effect.
A yet further object of the present invention is to resolve the above mentioned problems with the SOI-MOS device of the conventional art in FIG. 5, by providing an SOI-MOS device having a new structure and a production method for this device, that is widely applicable to semiconductor integrated circuits having a symmetrical structure of source and drain, and also prevents the body floating effect.
A still further object of the present invention is to provide an SOI-MOS device not utilizing new production technology, that can actively prevent the body floating effect and can easily be manufactured at a low cost with conventional production technology.
In order to achieve the above mentioned object of the invention, the semiconductor device has an MOS field effect transistor formed on the single crystalline silicon layer of the above mentioned SOI structure laminated along with an insulator on the handle wafer. The surface of the source region and the drain region of this MOS field effect transistor, are respectively connected to the source electrode and drain electrode by way of a contact hole (contact area) formed on a second insulator formed on the above mentioned single crystalline semiconductor layer. A recombination center region is formed connecting to the lower surface of the source region and drain region in the lower part of this contact hole of the single crystalline semiconductor layer.
Restated, as shown in FIG. 1, in the single crystalline Si layer 3 a recombination center region 20 is formed at the lower part of the contact area (contact hole) 19 electrically connected to a source diffusion region 9 and a drain diffusion region 10, and source electrode 12 and a drain electrode 13. Consequently, the holes generated within the single crystalline Si layer 3 just beneath the channel are injected into the recombination center region 20 by way of the single crystalline Si layer 3 beneath the source diffusion region 9 and eliminated so that the body floating effect is prevented.
This recombination center region 20 formed just beneath the drain diffusion region 10 might become a source of current leakage when drain voltage is applied, however the single crystalline Si layer 3 just beneath the drain diffusion region 10 is completely depleted by the application of a drain voltage so the leakage current flow path to the source diffusion region 9 is cut off and there is no possibility of current leakage flowing.
The operating principle of this invention resembles the operating principle of the junction field effect transistor (JFET). In a JFET, a voltage is applied to narrow the current path in the semiconductor region between the two matching junctions or in other words the amount of electrical current is regulated.
In contrast in this invention however, though the single crystalline Si layer 3 is cut off by the insulation layer 2, the current path, namely the amount of electrical current, is regulated by applying a voltage to one junction.
In this invention, it could be also said that, a JFET is embedded in the bottom of each source and drain of the SOI-MOS device.
The characteristics of the JFET embedded in the SOI-MOS, or in other words the elimination of holes on the source side (forward-direction hole current) and reverse-direction leakage current on the drain side, are determined by the thickness xcex94tso1 of single crystalline Si layer 3 for the matching JFET channel and also by junction length (channel length) w from the recombination center region 20 to the single crystalline Si layer 3 just below the gate, and the impurity concentration Na versus that junction length w.
A computer simulation to find the forward-direction hole current or in other words, the electrical current to eliminate the body floating effect is shown in FIG. 6A. The leakage current characteristics for the drain region are shown in FIGS. 6B.
As FIG. 6A and 6B clearly show, even though the junction length w from the recombination center region 20 to the single crystalline Si layer 3 just below the gate is an extremely small 50 nm, if the impurity concentration Na for the single crystalline Si layer 3 contacting the bottom of the junction is approximately 1017/cm3, then there is no possibility of leakage current occurring in the drain, a sufficient hole current can be maintained at the source side and the body floating effect can be eliminated.
In order to achieve the results of the above simulation, the thickness xcex94tso1 of single crystalline Si layer 30 for the matching JFET channel is extremely critical which in turn requires strict control of the source and drain junction depth. The ion implantation method is normally utilized in forming these junctions. However, the problem of channeling phenomenon occurs if the crystal displacement axis and the ion implantation angle match each other when the junctions are formed with ion implantation. In this phenomenon, impurity concentrations below 1017/cm3 in a region during ion implantation deviate widely from the Gauss distribution and distribute even deeper.
When this channeling phenomenon occurs during forming of the source and drain diffusion regions 9 and 10, the single crystalline Si layer 3 with a thickness xcex94tso1 contacting the bottom of the junction, becomes an entirely n-type layer, making problems likely to occur in forming the JFET channel. Accordingly, when using ion-implantation to form source and drain diffusion regions, the ion-implantation angle should preferably be performed at the xc2x120 degrees tilted from the perpendicular to the substrate surface.
To achieve strict control of the source and drain junction depth, separate ion-implantation may be performed for forming drain diffusion region and counter-conductive atoms as well as to compensate for regions formed deeper than needed due to channeling phenomenon.
The above description, utilized N-type MOS devices for making the explanation simple however needless to say, a P-type MOS devices may be used in the same way with only the conduction conductive type of the impurities being reversed.
The insulator layer and the single crystalline Si layer laminated on the handle wafer, the MOS field effect transistor formed on a single crystalline semiconductor layer, a second insulator layer formed on the single crystalline semiconductor layer, and the source and drain region of this MOS field effect transistor, and a specified portion of the single crystalline semiconductor layer below this source and drain region are formed with a (through) hole. The recombination center region may be formed from the source region, drain region as well as the single crystalline semiconductor layer below these regions by filling this hole with a metal film. In such a case, the recombination center region dimensions are specified by means of the metal semiconductor junction. The upper surface of the recombination center region must make contact with the lower surface of the source and drain diffusion regions. The lower surface of the recombination center region however, may contact the upper surface of the insulator layer or may be separated from this insulator layer. By keeping the insulator layer separate, the metal/Si surface area can be widened and a large contact area (surface area of recombination center region) can be secured even if the hole area is reduced.
This recombination center region may use a region conducting in the opposite direction of the source region and drain region or the recombination center region may also utilize a non-single crystalline silicon region such as Polycrystalline silicon.
The drain and source regions respectively have structures with regions that extend at the edge of the channel of the MOS field effect transistor yet are shallower than the source and drain and also in the same conductive type as the source and drain regions. These regions suppress the widening of the depletion layer and improve the breakdown voltage. In such cases, the concentration of impurities in a shallow region in the same conductive type as source and drain may be set lower than in the source and drain regions.
A semiconductor device may comprise a plurality of MOS field effect transistors mutually connected in serial or may comprise these field effect transistors connected in series with capacitor devices. In such cases, the recombination center region is formed at the opposite node of these capacitor devices, and is formed at the lower surface of the source region or drain region. Also in this case, the single crystalline semiconductor layer below the drain diffusion region is structured to reach the depletion region at the boundary of the insulator layer, while a drain voltage is being applied. Attaining the depletion region in this way, cuts off the current leakage flow path to the source diffusion region 9 so there is no possibility of current leakage flow occurring.
In the method for manufacturing the semiconductor device of this invention, after forming the SOI substrate by laminate-forming the insulator layer and the single crystalline semiconductor layer in sequence on the handle wafer, the method of the known art is then utilized to form the MOS field effect transistor on the single crystalline semiconductor layer, and a second insulator layer is further formed over the entire surface. A contact hole is formed in the second insulator layer and a portion of the MOS field effect transistor source and drain regions exposed. Ion implantation is performed by utilizing this contact hole and the recombination center region is formed in contact with the lower surface of the source region and drain region within the single crystalline semiconductor layer.
In other words, this contact hole is a connecting hole for electrically connecting the source and drain diffusion regions to the respective source electrode and drain electrodes. Ion implantation through this contact hole is performed to form the recombination center region to contact the source and drain diffusion regions within the single crystalline semiconductor layer beneath this contact hole.
The element used in the ion-implantation may be a fundamental element selected from a group consisting of group IV fundamental elements, halogen fundamental elements and rare earth metal fundamental elements. This ion-implantation forms a non-single crystalline region in contact with the lower surface of the source and drain regions inside the single crystalline semiconductor layer as described above. A section of the single crystalline semiconductor layer selected as the region to become amorphous during application of the accelerated voltage in the ion-implantation application becomes Polycrystalline due to heat treatment performed in subsequent processes but will not return to the single crystalline state.
After forming the SOI substrate, MOS field effect transistor, second insulator layer, and the source region and drain region of the MOS field effect transistor as related for the manufacturing method, a (through) contact hole is formed in the source region and drain region as well as in a specified portion of the single crystalline semiconductor layer below these source and drain regions. By filling this contact hole with a metallic layer, a recombination center region is formed inside the single crystalline semiconductor layer and in contact with the lower surface of the source and drain regions. In such cases, the recombination center region is separated from the single crystalline (Si) layer by a metal-semiconductor junction.
Many types of semiconductor devices can be configured for example such as asynchronous transmission mode devices and processor devices by utilizing the semiconductor device of this invention.